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Releasing in the second quarter of 2021, Dialog Semiconductor has developed new serial NOR 1 Mbit and 2 Mbit Flash memory configurations, which for power-conscious and space-constrained devices.
As usual, when a device is claiming the lowest power and energy in the industry, it is necessary to look deeper and analyze if this device can back up its claims. Before that, though, it might be beneficial to review the serial protocol SPI and how serial Flash compares with parallel Flash.
is a 4-wire communications protocol commonly used in many chip-to-chip applications. Three signals, including CLK, MOSI, and MISO, are shared between the client device and the server devices. (Author's note: You may see these terms referred to as “master/slave” devices, though the use of these terms is ).
The final wire, chip select, is unique to each server device.
SPI is used frequently for designs that require full-duplex communication between client and server by shifting one bit in each direction during each clock period.
Since NOR Flash is often read as configuration data before loading into active memory, what performance benefit does serial flash offer compared to parallel bus schemes?
Unlike the I2C standard, which SPI has no real standardization associated with its protocol.
One way to apply this benefit is by using high-speed clocks to multiply throughput. By increasing the clock speed and reducing the required number of traces in the PCB surface area the space-constrained embedded system can be optimized.
The SPI baud rates vary from vendor to vendor and This ability makes it possible to compete with parallel NOR Flash in performance, especially once factoring in other design considerations.
Embedded designs are, by definition, low power, and often run on battery power. A quick search at your electronics vendor of choice will reveal a rather significant tradeoff between parallel and serial flash devices in terms of power consumption.
For example, the from Microchip Technology is a 2 Mbit parallel NOR flash operating at 3V0/20 mA (max), as compared to
Beyond power, there is also a quest to reduce the size and cost of IoT devices. Parallel NOR will require a more complex PCB, both for breakout space on the board and matching the timing constraints between traces.
Now that the differences between SPI and parallel NOR have been considered, another comparison is serial NOR versus serial NOR.
The datasheet for the is not freely available yet; however, based on the released details, it seems that the AT25EU offers a deep power-down mode of 100 nA.
To create a comparison, another serial NOR to look at is the 2 Mbit Serial NOR from Macronix, which offers an identical voltage operating range as the AT25EU, however, it also has a deep-down power requirement of 70 nA to 350 nA.
From this specific comparison, it becomes apparent that the race for the lowest power SPI NOR Flash is a tight one.
Considering the target market for this chip, total energy utilized (power multiplied with time) is another metric that Dialog Semiconductor highlights as competitive with this device. The AT25EU also claims to perform a full erase in 10 ms (compare with a full erase of 2.7 to 8 seconds for the MX25R2035F), which can be beneficial.
Though this product appears to be holding up its claims, Dialog Semiconductor also has a variety of memory options available, including solutions for NXP's i.MX and STMicroelectronics microcontroller families, which, depending on the application and project, could add further benefits.